What is TSC scaling?

This feature, referred to as timestamp-counter scaling (TSC scaling), further extends the capability of virtual-machine monitor (VMM) software that employs the TSC-offsetting mechanism by allowing that software finer control over the value of the timestamp counter (TSC) read during guest virtual machine (VM) execution.

What is TSC in CPU?

The Time Stamp Counter (TSC) is a 64-bit register present on all x86 processors since the Pentium. It counts the number of CPU cycles since its reset.

What is constant TSC?

Constant TSC means that the TSC does not change with CPU frequency changes, however it does change on C state transitions. Invariant. As described in the Intel manual: “The invariant TSC will run at a constant rate in all ACPI P-, C- and T-states” Non-stop.

What is Rdtsc instruction?

The rdtsc (Read Time-Stamp Counter) instruction is used to determine how many CPU ticks took place since the processor was reset. Loads the current value of the processor’s time-stamp counter into the EDX:EAX registers. It is commonly used as a timing defense (anti-debugging technique).

What is the purpose of the time stamp counter in processors?

The time stamp counter can be used to time instructions accurately which can be exploited in the Meltdown and Spectre security vulnerabilities. However if this is not available other counters or timers can be used, as is the case with the ARM processors vulnerable to this type of attack.

What is Time Stamp Counter (TSC)?

The Time Stamp Counter ( TSC) is a 64-bit register present on all x86 processors since the Pentium. It counts the number of CPU cycles since its reset. The instruction RDTSC returns the TSC in EDX:EAX. In x86-64 mode, RDTSC also clears the upper 32 bits of RAX and RDX.

What is the RDTSCP time stamp?

RDTSCP returns the 64-bit time stamp in EDX:EAX and the 32-bit TSC_AUX signature value in ECX. The atomicity of RDTSCP ensures that no context switch can occur between the reads of the TSC and TSC_AUX values.